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1 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b mx29lv161d t/b datasheet
2 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b contents features ............................................................................................................................................................ 5 general description .................................................................................................................................... 6 pin configurations ........................................................................................................................................ 7 pin description ................................................................................................................................................ 9 block diagram ............................................................................................................................................... 10 block diagram description ..................................................................................................................... 1 1 block structure .......................................................................................................................................... 12 table 1-1. mx29lv161dt sector architecture ............................................................................. 12 table 1-2. mx29lv161db sector architecture ............................................................................ 13 bus operations ............................................................................................................................................. 14 table 2-1. bus operation ..................................................................................................................... 14 table 2-2. bus operation ..................................................................................................................... 15 functional operation descriptions .................................................................................................... 16 write commands/command sequences ...................................................................................... 16 requirements for reading array data ...................................................................................... 16 reset# operation ............................................................................................................................... 17 sector protect operation ............................................................................................................ 17 chip unprotect operation ............................................................................................................. 17 hardware write protect ................................................................................................................ 17 accelerated programming operation ..................................................................................... 17 temporary sector unprotect operation ............................................................................... 18 automatic select operation .......................................................................................................... 18 verify sector protect status operation ................................................................................ 18 data protection .................................................................................................................................. 18 low vcc write inhibit ........................................................................................................................ 18 write pulse "glitch" protection .................................................................................................. 19 logical inhibit ...................................................................................................................................... 19 power-up sequence .......................................................................................................................... 19 power-up write inhibit ..................................................................................................................... 19 power supply decoupling .............................................................................................................. 19 command operations .................................................................................................................................. 20 table 3. mx29lv161d t/b command definitions ........................................................................... 20 automatic programming of the memory array ..................................................................... 21 erasing the memory array ............................................................................................................. 21 sector erase ....................................................................................................................................... 22 chip erase ............................................................................................................................................. 23 sector erase suspend ..................................................................................................................... 23 sector erase resume ....................................................................................................................... 24 automatic select operations ....................................................................................................... 24 automatic select command sequence ...................................................................................... 24
3 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b read manufacturer id or device id ............................................................................................ 25 verify sector protection .............................................................................................................. 25 reset ...................................................................................................................................................... 25 common flash memory interface (cfi) mode .................................................................................... 26 query command and common flash interface (cfi) mode .................................................. 26 table 4-1. cfi mode: identifcation data values ........................................................................................ 26 table 4-2. cfi mode: system interface data values ................................................................................. 26 table 4-3. cfi mode: device geometry data values ................................................................................. 27 table 4-4. cfi mode: primary vendor-specifc extended query data values ........................................... 28 electrical characteristics ................................................................................................................... 29 absolute maximum stress ratings .............................................................................................. 29 operating temperature and voltage ......................................................................................... 29 dc characteristics ........................................................................................................................... 30 switching test circuit ..................................................................................................................... 31 switching test waveform .............................................................................................................. 31 ac characteristics ........................................................................................................................... 32 write command operation ........................................................................................................................ 33 figure 1. command write operation ............................................................................................... 33 read/reset operation ................................................................................................................................ 34 figure 2. read timing waveform ....................................................................................................... 34 figure 3. reset# timing waveform .................................................................................................. 35 erase/program operation ....................................................................................................................... 36 figure 4. automatic chip erase timing waveform ..................................................................... 36 figure 5. automatic chip erase algorithm flowchart ........................................................... 37 figure 6. automatic sector erase timing waveform ............................................................... 38 figure 7. automatic sector erase algorithm flowchart ................................................... 39 figure 8. erase suspend/resume flowchart ............................................................................. 40 figure 9. automatic program timing waveform ......................................................................... 41 figure 10. accelerated program timing diagram .................................................................... 41 figure 11. ce# controlled write timing waveform .................................................................. 42 figure 12. automatic programming algorithm flowchart ................................................... 43 sector protect/chip unprotect ........................................................................................................... 44 figure 13. sector protect/chip unprotect waveform (reset# control) ........................... 44 figure 14. in-system sector protect with reset#=vhv ........................................................... 45 figure 15. chip unprotect algorithm with reset#=vhv ........................................................... 46 table 5. temporary sector unprotect ........................................................................................ 47 figure 16. temporary sector unprotect waveform .............................................................. 47 figure 17. temporary sector unprotect flowchart ............................................................. 48 figure 18. silicon id read timing waveform ................................................................................. 49 write operation status ............................................................................................................................. 50 figure 19. data# polling timing waveform (during automatic algorithm) ...................... 50 figure 20. data# polling algorithm ................................................................................................ 51
4 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 21. toggle bit timing waveform (during automatic algorithm) ........................... 52 figure 22. toggle bit algorithm ....................................................................................................... 53 recommended operating conditions ................................................................................................... 54 erase and programming performance .............................................................................................. 55 data retention .............................................................................................................................................. 55 latch-up characteristics ........................................................................................................................ 55 tsop pin capacitance .................................................................................................................................. 55 ordering information ................................................................................................................................ 56 part name description ............................................................................................................................... 57 package information .................................................................................................................................. 58 revision history ........................................................................................................................................... 62
5 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b features general features ? word mode only - 1,048,576 x 16 ? sector structure - 8k-word x 1, 4k-word x 2, 16k-word x 1, 32k-word x 31 - provides sector protect function to prevent program or erase operation in the protected sector - provides chip unprotect function to allow code changing - provides temporary sector unprotect function for code changing in previously protected sector ? power supply operation - vcc 2.7 to 3.6 volt for read, erase, and program operations - vi/o 1.65v to 3.6v for input/output ? latch-up protected to 100ma from -1v to 1.5xvcc ? low vcc write inhibit : vcc vlko ? compatible with jedec standard - pinout and software compatible to single power supply flash performance ? high performance - fast access time: 90ns - word program time: 11us/word (typical) - fast erase time: 0.7s/sector, 15s/chip (typical) ? low power consumption - low active read current: 5ma (typical) at 5mhz - low standby current: 5ua (typical) ? 100,000 erase/program cycle (typical) ? 20 years data retention software features ? erase suspend/ erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased ? status reply - data# polling & toggle bits provide detection of program and erase operation completion ? support common flash interface (cfi) hardware features ? ready/busy# (ry/by#) output - provides a hardware method of detecting program and erase operation completion ? hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode ? wp#/acc - provide accelerated program capability package ? 48-pin tsop ? 48-ball csp (tfbga) ? 48-ball wfbga/xflga ? all pb-free devices are rohs compliant 16m-bit [1m x 16] 3v supply flash memory
6 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b general description mx29lv161dt/b is a 16mbit fash memory that can be organized as 1,048,576 words. these devices operate over a voltage range of 2.7v to 3.6v typically using a 3v power supply input. the memory array is divided into 32 equal 64 kilo byte blocks. however, depending on the device being used as a top-boot or bottom-boot device. the outermost two sectors at the top or at the bottom are respectively the boot blocks for this device. the mx29lv161dt/b is offered in a 48-pin tsop, 48-ball xflga/wfbga and a 48-ball csp(tfbga) jedec standard package. these packages are offered lead-free versions that are compliant to the rohs specifcations. the software algorithm used for this device also adheres to the jedec standard for single power supply devic - es. these fash parts can be programmed in system or on commercially available eprom/flash programmers. separate oe# and ce# (output enable and chip enable) signals are provided to simplify system design. when used with high speed processors, the 90ns read access time of this fash memory permits operation with minimal time lost due to system timing delays. the automatic write algorithm provided on macronix fash memories perform an automatic erase prior to write. the user only needs to provide a write command to the command register. the on-chip state machine automati - cally controls the program and erase functions including all necessary internal timings. since erase and write operations take much longer time than read operations, erase/write can be interrupted to perform read opera - tions in other sectors of the device. for this, erase suspend operation along with erase resume operation are provided. data# polling or toggle bits are used to indicate the end of the erase/write operation. these devices are manufactured at the macronix fabrication facility using the time tested and proven mxic's advance technology. this proprietary non-epi process provides a very high degree of latch-up protection for stresses up to 100 milliamperes on address and data pins from -1v to 1.5xvcc. with low power consumption and enhanced hardware and software features, this fash memory retains data reli - ably for at least twenty years. erase and programming functions have been tested to meet a typical specifcation of 100,000 cycles of operation.
7 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b pin configurations 48 tsop (standard type) (12mm x 20mm) a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we# reset# nc wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 vi/o gnd q15 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-ball csp (tfbga) (ball pitch =0.8mm, top view, balls facing down, 6 x 8 mm) a13 6 5 4 3 2 1 a b c d e f g h a9 a7 a3 we# ry/ by# a12 a8 wp#/ acc a17 a4 a14 a10 nc a18 a6 a2 a15 a11 re- set# a19 nc a5 a1 a16 q7 q5 q2 q0 a0 v i/o q15 q14 q12 q10 q8 q13 vcc q11 q9 gnd q6 q4 q3 q1 gnd ce# oe#
8 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b 48-ball wfbga (balls facing down, 4 x 6 x 0.75 mm) 48-ball xflga (balls facing down, 4 x 6 x 0.5 mm) a2 6 5 4 3 2 1 a b c d e f g h a1 gnd a0 ce# a4 a3 q8 oe# q0 a6 a7 a18 q10 q9 q1 a17 wp#/ acc a5 a19 q2 nc q3 nc we# re- set# vi/o nc q13 vcc q12 j k l a9 a10 a8 q4 q5 a11 a13 a12 q11 q6 a14 a15 a16 q7 gnd q14 q15 a2 6 5 4 3 2 1 a b c d e f g h a1 gnd a0 ce# a4 a3 q8 oe# q0 a6 a7 a18 q10 q9 q1 a17 wp#/ acc a5 a19 q2 nc q3 nc we# re- set# vi/o nc q13 vcc q12 j k l a9 a10 a8 q4 q5 a11 a13 a12 q11 q6 a14 a15 a16 q7 gnd q14 q15
9 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b pin description logic symbol 16 q0-q15 ry/by# a0-a19 vcc gnd ce# oe# we# reset# wp#/acc 20 v i/o symbol pin name a0~a19 address input q0~q15 data input/output ce# chip enable input we# write enable input reset# hardware reset pin/sector protect unlock oe# output enable input ry/by# ready/busy output vcc power supply pin (2.7v~3.6v) gnd ground pin vi/o power supply for input/output wp#/acc hardware write protect/acceleration pin nc pin not connected internally
10 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b block diagram control input logic program/erase high voltage write state machine (wsm) state register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15 a0-am am: msb address ce# oe# we# reset# wp#/acc
11 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b block diagram description the block diagram on page 10 illustrates a simplifed architecture of mx29lv161d t/b. each block in the block diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the memory array. the "control input logic" block receives input pins ce#, oe#, we#, reset# and wp#/acc. it creates internal timing control signals according to the input pins and outputs to the "address latch and buffer" to latch the external address pins a0-am(a19). the internal addresses are output from this block to the main ar - ray and decoders composed of "x-decoder", "y-decoder", "y-pass gate", and "flash array". the x- decoder decodes the word-lines of the fash array, while the y-decoder decodes the bit-lines of the fash ar - ray. the bit lines are electrically connected to the "sense amplifier" and "pgm data hv" selectively through the y-pass gates. sense amplifers are used to read out the contents of the fash memory, while the "pgm data hv" block is used to selectively deliver high power to bit-lines during programming. the "i/o buffer" controls the input and output on the q0-q15 pads. during read operation, the i/o buffer receives data from sense ampli - fers and drives the output pads accordingly. in the last cycle of program command, the i/o buffer transmits the data on q0-q15 to "program data latch", which controls the high power drivers in "pgm data hv" to se - lectively program the bits in a word according to the user input pattern. the "program/erase high voltage" block comprises the circuits to generate and deliver the necessary high voltage to the "x-decoder", "flash array", and "pgm data hv" block. the logic control module comprises of the "write state machine(wsm)", "state register", "command data decoder", and "command data latch". when the user issues a command by toggling we#, the command on q0-q15 is latched in the command data latch and is decoded by the command data decoder. the state register receives the command and records the current state of the device. the wsm implements the internal algorithms for pro - gram or erase according to the current command state by controlling each block in the block diagram.
12 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b table 1-1. mx29lv161dt sector architecture block structure the main fash memory array can be organized as 1m words. the details of the address ranges and the cor - responding sector addresses are shown in table 1-1&1-2. table 1-1. shows the sector architecture for the top boot part, whereas table 1-2. shows the sector architecture for the bottom boot part. sector size word mode (kwords) sector sector address a19-a12 address range word mode (x16) 32 sa0 00000xxx 000000h-07fffh 32 sa1 00001xxx 008000h-0ffffh 32 sa2 00010xxx 010000h-17fffh 32 sa3 00011xxx 018000h-01ffffh 32 sa4 00100xxx 020000h-027fffh 32 sa5 00101xxx 028000h-02ffffh 32 sa6 00110xxx 030000h-037fffh 32 sa7 00111xxx 038000h-03ffffh 32 sa8 01000xxx 040000h-047fffh 32 sa9 01001xxx 048000h-04ffffh 32 sa10 01010xxx 050000h-057fffh 32 sa11 01011xxx 058000h-05ffffh 32 sa12 01100xxx 060000h-067fffh 32 sa13 01101xxx 068000h-06ffffh 32 sa14 01110xxx 070000h-077fffh 32 sa15 01111xxx 078000h-07ffffh 32 sa16 10000xxx 080000h-087fffh 32 sa17 10001xxx 088000h-08ffffh 32 sa18 10010xxx 090000h-097fffh 32 sa19 10011xxx 098000h-09ffffh 32 sa20 10100xxx 0a0000h-0a7fffh 32 sa21 10101xxx 0a8000h-0affffh 32 sa22 10110xxx 0b0000h-0b7fffh 32 sa23 10111xxx 0b8000h-0bffffh 32 sa24 11000xxx 0c0000h-0c7fffh 32 sa25 11001xxx 0c8000h-0cffffh 32 sa26 11010xxx 0d0000h-0d7fffh 32 sa27 11011xxx 0d8000h-0dffffh 32 sa28 11100xxx 0e0000h-0e7fffh 32 sa29 11101xxx 0e8000h-0effffh 32 sa30 11110xxx 0f0000h-0f7fffh 16 sa31 111110xx 0f8000h-0fbfffh 4 sa32 11111100 0fc000h-0fcfffh 4 sa33 11111101 0fd000h-0fdfffh 8 sa34 1111111x 0fe000h-0fffffh
13 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b table 1-2. mx29lv161db sector architecture sector size word mode (kwords) sector sector address a19-a12 address range word mode (x16) 8 sa0 0000000x 000000h-001fffh 4 sa1 00000010 002000h-002fffh 4 sa2 00000011 003000h-003fffh 16 sa3 000001xx 004000h-007fffh 32 sa4 00001xxx 008000h-00ffffh 32 sa5 00010xxx 010000h-017fffh 32 sa6 00011xxx 018000h-01ffffh 32 sa7 00100xxx 020000h-027fffh 32 sa8 00101xxx 028000h-02ffffh 32 sa9 00110xxx 030000h-037fffh 32 sa10 00111xxx 038000h-03ffffh 32 sa11 01000xxx 040000h-047fffh 32 sa12 01001xxx 048000h-04ffffh 32 sa13 01010xxx 050000h-057fffh 32 sa14 01011xxx 058000h-05ffffh 32 sa15 01100xxx 060000h-067fffh 32 sa16 01101xxx 068000h-06ffffh 32 sa17 01110xxx 070000h-077fffh 32 sa18 01111xxx 078000h-07ffffh 32 sa19 10000xxx 080000h-087fffh 32 sa20 10001xxx 088000h-08ffffh 32 sa21 10010xxx 090000h-097fffh 32 sa22 10011xxx 098000h-09ffffh 32 sa23 10100xxx 0a0000h-0a7fffh 32 sa24 10101xxx 0a8000h-0affffh 32 sa25 10110xxx 0b0000h-0b7fffh 32 sa26 10111xxx 0b8000h-0bffffh 32 sa27 11000xxx 0c0000h-0c7fffh 32 sa28 11001xxx 0c8000h-0cffffh 32 sa29 11010xxx 0d0000h-0d7fffh 32 sa30 11011xxx 0d8000h-0dffffh 32 sa31 11100xxx 0e0000h-0e7fffh 32 sa32 11101xxx 0e8000h-0effffh 32 sa33 11110xxx 0f0000h-0f7fffh 32 sa34 11111xxx 0f8000h-0fffffh
14 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b bus operations table 2-1. bus operation notes: 1. all sectors will be unprotected if wp#/acc=vhv. 2. the one outmost boot sectors are protected if wp#/acc=vil. 3. when wp#/acc = vih, the protection conditions of the one outmost boot sectors depend on previous protec - tion conditions."sector/sector block protection and unprotection" describes the protect and unprotect meth - od. 4. q0~q15 are input (din) or output (dout) pins according to the requests of command sequence, sector pro - tection, or data polling algorithm. mode select reset# ce# we# oe# address data i/o q0~q7 wp#/acc device reset l x x x x highz l/h standby mode vcc0.3v vcc 0.3v x x x highz h output disable h l h h x highz l/h read mode h l h l ain dout l/h write (note1) h l l h ain din note3 accelerate program h l l h ain din vhv temporary sector unprotect vhv x x x ain din note3 sector protect (note2) vhv l l h sector address, a6=l, a1=h, a0=l din, dout l/h chip unprotect (note2) vhv l l h sector address, a6=h, a1=h, a0=l din, dout note3
15 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b notes: 1. sector unprotected code:00h. sector protected code:01h. 2. am: msb of address. table 2-2. bus operation item control input am to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 q0 ~ q7 q8 ~ q15 ce# we# oe# sector lock status verifcation l h l sa x v hv x l x h l 01h or 00h (note 1) x read silicon id manufacturer code l h l x x v hv x l x l l c2h x read silicon id mx29lv161dt l h l x x v hv x l x l h c4h 22h read silicon id mx29lv161db l h l x x v hv x l x l h 49h 22h
16 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b write commands/command sequences to write a command to the device, system must drive we# and ce# to vil, and oe# to vih. in a command cycle, all addresses are latched at the later falling edge of ce# and we#, and all data are latched at the earlier rising edge of ce# and we#. figure 1 illustrates the ac timing waveform of a write command, and table 3 defnes all the valid command sets of the device. system is not allowed to write invalid commands not defned in this datasheet. writing an invalid command will bring the device to an undefned state. requirements for reading array data read array action is to read the data stored in the array. while the memory device is in powered up or has been reset, it will automatically enter the status of read array. if the microprocessor wants to read the data stored in ar - ray, it has to drive ce# (device enable control pin) and oe# (output control pin) as vil, and input the address of the data to be read into address pins at the same time. after a period of read cycle (tce or taa), the data being read out will be displayed on output pins for microprocessor to access. if ce# or oe# is vih, the output will be in tri-state, and there will be no data displayed on output pin at all. after the memory device completes embedded operation (automatic erase or program), it will automatically re - turn to the status of read array, and the device can read the data in any address in the array. in the process of erasing, if the device receives the erase suspend command, erase operation will be stopped temporarily after a period of time no more than tready1 and the device will return to the status of read array. at this time, the device can read the data stored in any address except the sector being erased in the array. in the status of erase sus - pend, if user wants to read the data in the sectors being erased, the device will output status data onto the out - put. similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. the device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. in program or erase operation, the programming or erasing failure causes q5 to go high. 2. the device is in auto select mode or cfi mode. in the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. functional operation descriptions
17 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b reset# operation driving reset# pin low for a period more than trp will reset the device back to read mode. if the device is in program or erase operation, the reset operation will take at most a period of tready1 for the device to return to read array mode. before the device returns to read array mode, the r y/by# pin remains low (busy status). when reset# pin is held at gnd 0.3v, the device consumes standby current(isb).however, device draws larg - er current if reset# pin is held at vil but not within gnd 0.3v. it is recommended that the system to tie its reset signal to reset# pin of fash memory, so that the fash memo - ry will be reset during system reset and allows system to read boot code from fash memory . sector protect operation when a sector is protected, program or erase operation will be disabled on that protected sector. mx29lv161d t/b provides two methods for sector protection. once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting reset# pin at vhv. refer to temporary sector unprotect operation for further details. the frst method is by applying vhv on reset# pin. refer to figure 12 for timing diagram and figure 13 for the algorithm for this method. the other method is asserting vhv on a9 and oe# pins, with a6 and ce# at vil. the protection operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. chip unprotect operation mx29lv161d t/b provides two methods for chip unprotect. the chip unprotect operation unprotects all sectors within the device. it is recommended to protect all sectors before activating chip unprotect mode. all sectors are unprotected when shipped from the factory. the frst method is by applying vhv on reset# pin. refer to figure 12 for timing diagram and figure 14 for al - gorithm of the operation. the other method is asserting vhv on a9 and oe# pins, with a6 at vih and ce# at vil. the unprotect operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. hardware write protect by driving the wp#/acc pin low, the outermost one boot sectors are protected from all erase/program opera - tions. if wp#/acc is held high (vih), these one outermost sectors revert to their previously protected/unpro - tected status. accelerated programming operation by applying high voltage (vhv) to the wp#/acc pin, the device will enter the accelerated programming mode. this mode permits the system to skip the normal command unlock sequences and program word locations di -
18 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b rectly. typically, this mode provides a 30% reduction in overall programming times. during accelerated programming, the current drawn from the wp#/acc pin is no more than icp1. temporary sector unprotect operation system can apply reset# pin at vhv to place the device in temporary unprotect mode. in this mode, previously protected sectors can be programmed or erased just as it is unprotected. the devices return to normal operation once vhv is removed from reset# pin and previously protected sectors are again protected. automatic select operation when the device is in read array mode, erase-suspended read array mode or cfi mode, user can issue read silicon id command to enter read silicon id mode. after entering read silicon id mode, user can query several silicon ids continuously and does not need to issue read silicon id mode again. when a0 is low, device will out - put macronix manufacture id c2h. when a0 is high, device will output device id. in read silicon id mode, issu - ing reset command will reset device back to read array mode or erase-suspended read array mode. another way to enter read silicon id is to apply high voltage on a9 pin with ce#, oe#, a6 and a1 at vil. while the high voltage of a9 pin is discharged, device will automatically leave read silicon id mode and go back to read array mode or erase-suspended read array mode. when a0 is low, device will output macronix manufacture id c2h. when a0 is high, device will output device id. verify sector protect status operation mx29lv161d t/b provides hardware sector protection against program and erase operation for protected sec - tors. the sector protect status can be read through sector protect verify command. this method requires vhv on a9 pin, vih on we# and a1 pins, vil on ce#, oe#, a6 and a0 pins, and sector address on a12 to am pins. if the read out data is 01h, the designated sector is protected. oppositely, if the read out data is 00h, the designated sector is not protected. data protection to avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. besides, only after successful completion of the specifed command sets will the device begin its erase or program operation. other features to protect the data from accidental alternation are described as followed. low vcc write inhibit the device refuses to accept any write command when vcc is less than vlko. this prevents data from spuriously altered. the device automatically resets itself when vcc is lower than vlko and write cycles are ignored until vcc is greater than vlko. system must provide proper signals on control pins after vcc is larger than vlko to avoid un - intentional program or erase operation.
19 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b write pulse "glitch" protection ce#, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. logical inhibit a valid write cycle requires both ce# and we# at vil with oe# at vih. write cycle is ignored when either ce# at vih, we# at vih, or oe# at vil. power-up sequence upon power up, mx29lv161d t/b is placed in read array mode. furthermore, program or erase operation will begin only after successful completion of specifed command sequences. power-up write inhibit when we#, ce# is held at vil and oe# is held at vih during power up, the device ignores the frst command on the rising edge of we#. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect.
20 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b table 3. mx29lv161d t/b command definitions notes: 1. device id : mx29lv161dt: 22c4h; mx29lv161db: 2249h. 2. for sector protect verify result, xx00h/00h means sector is not protected, xx01h/01h means sector has been protected. 3. sector protect command is valid during vhv at reset# pin, vih at a1 pin and vil at a0, a6 pins. the last bus cycle is for protect verify. 4. it is not allowed to adopt any other code which is not in the above command defnition table. command operations command read mode reset mode automatic select program chip erase manifacture id device id sector protect verify 1st bus cycle addr addr xxx 555 555 555 555 555 data data f0 aa aa aa aa aa 2nd bus cycle addr 2aa 2aa 2aa 2aa 2aa data 55 55 55 55 55 3rd bus cycle addr 555 555 555 555 555 data 90 90 90 a0 80 4th bus cycle addr x00 x01 (sector) x02 address 555 data c2h id 00/01 data aa 5th bus cycle addr 2aa data 55 6th bus cycle addr 555 data 10 command sector erase cfi read erase suspend erase resume 1st bus cycle addr 555 55 xxx xxx data aa 98 b0 30 2nd bus cycle addr 2aa data 55 3rd bus cycle addr 555 data 80 4th bus cycle addr 555 data aa 5th bus cycle addr 2aa data 55 6th bus cycle addr sector data 30
21 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b command operations (cont'd) automatic programming of the memory array the mx29lv161d t/b provides the user the ability to program the memory array in word mode. as long as the users enters the correct cycle defned in the table 3 (including 2 unlock cycles and the a0h program command), any word data provided on the data lines by the system will automatically be programmed into the array at the specifed location. after the program command sequence has been executed, the internal write state machine (wsm) automatically executes the algorithms and timings necessary for programming and verifcation, which includes generating suit - able program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do not pass verifcation or have low margins. the internal controller protects cells that do pass verifcation and mar - gin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells continue to be programmed. with the internal wsm automatically controlling the programming process, the user only needs to enter the pro - gram command and data once. programming will only change the bit status from "1" to "0". it is not possible to change the bit status from "0" to "1" by programming. this can only be done by an erase operation. furthermore, the internal write verifcation only checks and detects errors in cases where a "1" is not successfully programmed to "0". any commands written to the device during programming will be ignored except hardware reset, which will termi - nate the program operation after a period of time no more than tready1. when the embedded program algorithm is complete or the program operation is terminated by a hardware reset, the device will return to read mode. after the embedded program operation has begun, the user can check for completion by reading the following bits in the status register: *1: when an attempt is made to program a protected sector, the program operation will abort thus preventing any data changes in the protected sector. q7 will output complement data and q6 will toggle briefy (1us or less) before aborting and returning the device to read mode. *2: ry/by# is an open drain output pin and should be connected to vcc through a high value pull-up resistor. *3: the status "in progress" means both program and erase-suspended program mode. erasing the memory array there are two types of erase operations performed on the memory array -- sector erase and chip erase. in the sector erase operation, one or more selected sectors may be erased simultaneously. in the chip erase opera - tion, the complete memory array is erased except for any protected sectors. status q7*1 q6*1 q5 ry/by# *2 in progress *3 q7# toggling 0 0 finished q7 stop toggling 0 1 exceed time limit q7# toggling 1 0
22 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b sector erase the sector erase operation is used to clear data within a sector by returning all of its memory locations to the "1" state. it requires six command cycles to initiate the erase operation. the frst two cycles are "unlock cycles", the third is a confguration cycle, the fourth and ffth are also "unlock cycles", and the sixth cycle is the sector erase command. after the sector erase command sequence has been issued, an internal 50us time-out counter is started. until this counter reaches zero, additional sector addresses and sector erase commands may be is - sued thus allowing multiple sectors to be selected and erased simultaneously. after the 50us time-out counter has expired, no new commands will be accepted and the embedded sector erase operation will begin. note that the 50us timer-out counter is restarted after every erase command sequence. if the user enters any command other than sector erase or erase suspend during the time-out period, the erase operation will abort and the de - vice will return to read mode. after the embedded sector erase operation begins, all commands except erase suspend will be ignored. the only way to interrupt the operation is with an erase suspend command or with a hardware reset. the hardware reset will completely abort the operation and return the device to read mode. note : 1. the q3 status bit is the time-out indicator. when q3=0, the time-out counter has not yet reached zero and a new sector erase command may be issued to specify the address of another sector to be erased. when q3=1, the time-out counter has expired and the sector erase operation has already begun. erase suspend is the only valid command that may be issued once the embedded erase operation is underway . 2. ry/by# is an open drain output pin and should be connected to vcc through a high value pull-up resistor. 3. when an attempt is made to erase only protected sector(s), the program operation will abort thus preventing any data changes in the protected sector(s). q7 will output its complement data and q6 will toggle briefy (100us or less) before aborting and returning the device to read mode. if unprotected sectors are also specifed, however, they will be erased normally and the protected sector(s) will remain unchanged. 4. q2 is a localized indicator showing a specifed sector is undergoing erase operation or not. q2 toggles when user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase suspend mode). when a sector has been completely erased, q2 stops toggling at the sector even when the device is still in erase operation for remaining selected sectors. at that circumstance, q2 will still toggle when device is read at any other sector that remains to be erased. command operations (cont'd) the system can determine the status of the embedded sector erase operation by the following methods: status q7 q6 q5 q3 (*1) q2 ry/by#(*2) time-out period 0 toggling 0 0 toggling 0 in progress 0 toggling 0 1 toggling 0 finished 1 stop toggling 0 1 1 1 exceeded time limit 0 toggling 1 1 toggling 0
23 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b chip erase the chip erase operation is used erase all the data within the memory array. all memory cells containing a "0" will be returned to the erased state of "1". this operation requires 6 write cycles to initiate the action. the frst two cycles are "unlock" cycles, the third is a confguration cycle, the fourth and ffth are also "unlock" cycles, and the sixth cycle initiates the chip erase operation. during the chip erase operation, no other software commands will be accepted, but if a hardware reset is re - ceived or the working voltage is too low, that chip erase will be terminated. after chip erase, the chip will auto - matically return to read mode. the system can determine the status of the embedded chip erase operation by the following methods: *1: ry/by# is an open drain output pin and should be connected to vcc through a high value pull-up resistor. after beginning a sector erase operation, erase suspend is the only valid command that may be issued. if sys - tem issues an erase suspend command during the 50us time-out period following a sector erase command, the time-out period will terminate immediately and the device will enter erase-suspended read mode. if the system issues an erase suspend command after the sector erase operation has already begun, the device will not enter erase-suspended read mode until tready1 time has elapsed. the system can determine if the device has en - tered the erase-suspended read mode through q6, q7, and ry/by#. after the device has entered erase-suspended read mode, the system can read or program any sector(s) ex - cept those being erased by the suspended erase operation. reading any sector being erased or programmed will return the contents of the status register. whenever a suspend command is issued, user must issue a re - sume command and check q6 toggle bit status, before issue another erase command. the system can use the status register bits shown in the following table to determine the current state of the device: sector erase suspend when the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon id, sector protect verify, program, cfi query and erase resume. command operations (cont'd) status q7 q6 q5 q2 ry/by# *1 in progress 0 toggling 0 toggling 0 finished 1 stop toggling 0 1 1 exceed time limit 0 toggling 1 toggling 0 status q7 q6 q5 q3 q2 ry/by# erase suspend read in erase suspended sector 1 no toggle 0 n/a toggle 1 erase suspend read in non-erase suspended sector data data data data data 1 erase suspend program in non-erase suspended sector q7# toggle 0 n/a n/a 0
24 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b command operations (cont'd) sector erase resume the sector erase resume command is valid only when the device is in erase-suspended read mode. after erase resumes, the user can issue another ease suspend command, but there should be a 4ms interval be - tween ease resume and the next erase suspend command. if the user enters an infnite suspend-resume loop, or suspend-resume exceeds 1024 times, erase times will increase dramatically . automatic select operations when the device is in read mode, erase-suspended read mode, or cfi mode, the user can issue the automat - ic select command shown in table 3 (two unlock cycles followed by the automatic select command 90h) to enter automatic select mode. after entering automatic select mode, the user can query the manufacturer id, device id, or sector protected status multiple times without issuing a new automatic select command. while in automatic select mode, issuing a reset command (f0h) will return the device to read mode (or erase- suspended read mode if erase-suspend was active). another way to enter automatic select mode is to use one of the bus operations shown in table 2-2. bus operation. after the high voltage (vhv) is removed from the a9 pin, the device will automatically return to read mode or erase-suspended read mode. automatic select command sequence automatic select mode is used to access the manufacturer id, device id and to verify whether or not a sector is protected. the automatic select mode has four command cycles. the frst two are unlock cycles, and followed by a specifc command. the fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. the reset command is necessary to exit the automatic se - lect mode and back to read array. the following table shows the identifcation code with corresponding address. after entering automatic select mode, no other commands are allowed except the reset command. address (hex) data (hex) representation manufacturer id x00 00c2 device id x01 22c4/2249 top/bottom boot sector sector protect verify (sector address) x 02 00/01 unprotected/protected
25 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b read manufacturer id or device id the manufacturer id (identifcation) is a unique hexadecimal number assigned to each manufacturer by the je - dec committee. each company has its own manufacturer id, which is different from the id of all other compa - nies. the number assigned to macronix is c2h. the device id is a unique hexadecimal number assigned by the manufacturer for each one of the fash devices made by that manufacturer. the above two id types are stored in a 16-bit register on the fash device -- eight bits for each id. this register is normally read by the user or by the programming machine to identify the manufacturer and the specifc device. after entering automatic select mode, performing a read operation with a1 & a0 held low will cause the device to output the manufacturer id on the data i/o (q7 to q0) pins. performing a read operation with a1 low and a0 high will cause the device to output the device id. verify sector protection after entering automatic select mode, performing a read operation with a1 held high and a0, a6 held low and the address of the sector to be checked applied to a19 to a12, data bit q0 will indicate the protected status of the addressed sector. if q0 is high, the sector is protected. conversely, if q0 is low, the sector is unprotected. reset in the following situations, executing reset command will reset device back to read array mode: ? among erase command sequence (before the full command set is completed) ? sector erase time-out period ? erase fail (while q5 is high) ? among program command sequence (before the full command set is completed, erase-suspended program included) ? program fail (while q5 is high, and erase-suspended program fail is included) ? read silicon id mode ? sector protect verify ? cfi mode while device is at the status of program fail or erase fail (q5 is high), user must issue reset command to reset device back to read array mode. while the device is in read silicon id mode, sector protect verify or cfi mode, user must issue reset command to reset device back to read array mode. when the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig - nore reset command. command operations (cont'd)
26 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b table 4-1. cfi mode: identifcation data values (all values in these tables are in hexadecimal) table 4-2. cfi mode: system interface data values common flash memory interface (cfi) mode query command and common flash interface (cfi) mode mx29lv161d t/b features cfi mode. host system can retrieve the operating characteristics, structure and ven - dor-specifed information such as identifying information, memory size, byte/word confguration, operating volt - ages and timing information of this device by cfi mode. if the system writes the cfi query command "98h", to address "55h"/"aah", the device will enter the cfi query mode, any time the device is ready to read array data. the system can read cfi information at the addresses given in table 4. once user enters cfi query mode, user can not issue any other commands except reset command. the reset command is required to exit cfi mode and go back to the mode before entering cfi. the system can write the cfi query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. description address (h) (word mode) data (h) query-unique ascii string "qry" 10 0051 11 0052 12 0059 primary vendor command set and control interface id code 13 0002 14 0000 address for primary algorithm extended query table 15 0040 16 0000 alternate vendor command set and control interface id code 17 0000 18 0000 address for alternate algorithm extended query table 19 0000 1a 0000 description address (h) (word mode) data (h) vcc supply minimum program/erase voltage 1b 0027 vcc supply maximum program/erase voltage 1c 0036 vpp supply minimum program/erase voltage 1d 0000 vpp supply maximum program/erase voltage 1e 0000 typical timeout per single word/byte write, 2 n us 1f 0004 typical timeout for maximum-size buffer write, 2 n us 20 0000 typical timeout per individual block erase, 2 n ms 21 000a typical timeout for full chip erase, 2 n ms 22 0000 maximum timeout for word/byte write, 2 n times typical 23 0005 maximum timeout for buffer write, 2 n times typical 24 0000 maximum timeout per individual block erase, 2 n times typical 25 0004 maximum timeout for chip erase, 2 n times typical 26 0000
27 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b table 4-3. cfi mode: device geometry data values description address (h) (word mode) data (h) device size = 2 n in number of bytes (mx29lv161d) 27 0015 flash device interface description (01=asynchronous x16) 28 0001 29 0000 maximum number of bytes in buffer write = 2 n (not support) 2a 0000 2b 0000 number of erase regions within device 2c 0004 index for erase bank area 1 [2e,2d] = # of same-size sectors in region 1-1 [30, 2f] = sector size in multiples of 256-bytes 2d 0000 2e 0000 2f 0040 30 0000 index for erase bank area 2 31 0001 32 0000 33 0020 34 0000 index for erase bank area 3 35 0000 36 0000 37 0080 38 0000 index for erase bank area 4 (for mx29lv160d) 39 001e 3a 0000 3b 0000 3c 0001
28 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b table 4-4. cfi mode: primary vendor-specifc extended query data values description address (h) (word mode) data (h) query - primary extended table, unique ascii string, pri 40 0050 41 0052 42 0049 major version number, ascii 43 0031 minor version number, ascii 44 0030 unlock recognizes address (0= recognize, 1= don't recognize) 45 0000 erase suspend (2= to both read and program) 46 0002 sector protect (n= # of sectors/group) 47 0001 temporary sector unprotect (1=supported) 48 0001 sector protect/chip unprotect scheme 49 0004 simultaneous r/w operation (0=not supported) 4a 0000 burst mode (0=not supported) 4b 0000 page mode (0=not supported) 4c 0000 minimum acceleration supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4d 00a5 maximum acceleration supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4e 00b5 top/bottom boot block indicator 02h=bottom boot device 03h=top boot device 4f 0002/0003
29 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b absolute maximum stress ratings operating temperature and voltage electrical characteristics note: 1. minimum voltage may undershoot to -2v during transition and for less than 20ns during transitions. 2. maximum voltage may overshoot to vcc+2v during transition and for less than 20ns during transitions. commercial (c) grade surrounding temperature (t a ) 0c to +70c industrial (i) grade surrounding temperature (t a ) -40c to +85c vcc supply voltages vcc range +2.7v to 3.6v vi/o supply voltages vi/o range 1.65v to 3.6v surrounding temperature with bias -65 o c to +125 o c storage temperature -65 o c to +150 o c voltage range vcc -0.5v to +4.0v vi/o -0.5v to +4.0v reset#, a9 and oe# -0.5v to +10.5v the other pins -0.5v to vcc +0.5v output short circuit current (less than one second) 200 ma
30 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b dc characteristics symbol description min. typ. max. remark iilk input leak 1.0ua iilk9 a9 leak 35ua a9=10.5v iolk output leak 1.0ua icr1 read current(5mhz) 5ma 12ma ce#=vil, oe#=vih icr2 read current(1mhz) 2ma 4ma ce#=vil, oe#=vih icw write current 15ma 30ma ce#=vil, oe#=vih, we#=vil isb standby current 5ua 15ua vcc=vcc max, other pins disable isbr reset current 5ua 15ua vcc=vccmax, reset# enable, other pins disable isbs sleep mode current 5ua 15ua icp1 accelerated pgm current, wp#/acc pin 5ma 10ma ce#=vil, oe#=vih icp2 accelerated pgm current, vcc pin 15ma 30ma ce#=vil, oe#=vih vil input low voltage -0.1v 0.3xvi/o vih input high voltage 0.7 x vi/o vi/o + 0.3v vhv very high voltage for hardware protect/ unprotect/auto select/temporary unprotect 9.5v 10.5v vol output low voltage 0.15 x v i/o iol=100ua voh output high voltage 0.85 x v i/o ioh=-100ua vlko low vcc lock-out voltage 2.3v 2.5v
31 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b switching test waveform switching test circuit 2 1 v i/o test points v i/o 0.0v output input 2 1 v i/o test condition output load capacitance,cl : 30pf(90ns) r1=r2=25k ? rise/fall times : 5ns in/out reference levels :v i/o / 2 device under test cl r1 vi/o out r2
32 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b ac characteristics symbol description min. typ. max. unit taa valid data output after address 90 ns tce valid data output after ce# low 90 ns toe valid data output after oe# low 40 ns tdf data output foating after oe# high 30 ns toh output hold time from the earliest rising edge of address, ce#, oe# 0 ns trc read period time 90 ns tsrw latency between read and write operation (*note 1) 45 ns twc write period time 90 ns tcwc command write period time 90 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 35 ns tdh data hold time 0 ns tvcs vcc setup time 200 us tcs chip enable setup time 0 ns tch chip enable hold time 0 ns toes output enable setup time 0 ns toeh output enable hold time read 0 ns toggle & data# polling 10 ns tws we# setup time 0 ns twh we# hold time 0 ns tcep ce# pulse width 35 ns tceph ce# pulse width high 30 ns twp we# pulse width 35 ns twph we# pulse width high 30 ns tbusy program/erase active time by ry/by# 90 ns tghwl read recover time before write 0 ns tghel read recover time before write 0 ns twhwh1 program operation 11 us twhwh1 accelerated program operation 7 210 us twhwh2 sector erase operation 0.7 sec tbal sector add hold time 50 us * note 1: sampled only, not 100% tested.
33 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 1. command write operation write command operation addresses ce# oe# we# din tds ta h data tdh tcs tch tcwc twph twp toes ta s vih vil vih vil vih vil vih vil vih vil va va: valid address
34 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b read/reset operation figure 2. read timing waveform addresses ce# oe# ta a we# vih vil vih vil vih vil vih vil voh vol high z high z data valid to e toeh tdf tce trc outputs to h add valid tsrw
35 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 3. reset# timing waveform ac characteristics trh trb1 trp2 trp1 tready2 tready1 ry/by# ce#, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# ce#, oe# trb2 we# reset# item description setup speed unit trp1 reset# pulse width (during automatic algorithms) min 10 us trp2 reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read min 70 ns trb1 ry/by# recovery time (to ce#, oe# go low) min 0 ns trb2 ry/by# recovery time (to we# go low) min 50 ns tready1 reset# pin low (during automatic algorithms) to read or write max 20 us tready2 reset# pin low (not during automatic algorithms) to read or write max 500 ns
36 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b erase/program operation figure 4. automatic chip erase timing waveform twc address oe# ce# 55h 2aah sa 10h in progress complete va va ta s ta h sa: 555h for chip erase tghwl tch twp tds tdh read status last 2 erase command cycles tbusy trb tcs twph we# data ry/by#
37 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 5. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto chip erase completed
38 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 6. automatic sector erase timing waveform twc address oe# ce# 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h sector address n ta s ta h tbal tghwl tch twp tds tdh twhwh2 read status last 2 erase command cycle tbusy trb tcs twph we# data ry/by# 30h
39 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 7. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto sector erase completed no last sector to erase ? yes yes no data=ffh ?
40 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 8. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled ? erase suspend yes no write data 30h continue erase reading or programming end ? read array or program another erase suspend ? no yes yes no erase resume
41 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 9. automatic program timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tch twp tds tdh twhwh1 last 2 read status cycle last 2 program command cycle tbusy trb tcs twph we# data ry/by# figure 10. accelerated program timing diagram wp#/acc 250ns 250ns vhv (9.5v ~ 10.5v) vil or vih vil or vih
42 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 11. ce# controlled write timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tcep tds tdh twhwh1 or twhwh2 tbusy tceph we# data ry/by#
43 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 12. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes read again data: program data? yes auto program completed data# polling algorithm or toggle bit algorithm next address last address to be programed ? no no
44 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b sector protect/chip unprotect figure 13. sector protect/chip unprotect waveform (reset# control) 150us: sector protect 15ms: chip unprotect 1us vhv vih data sa, a6 a1, a0 ce# we# oe# va va va status va: valid address 40h 60h 60h verification reset#
45 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 14. in-system sector protect with reset#=vhv start retry count=0 reset#=vhv wait 1us write sector address with [a6,a1,a0]:[0,1,0] data: 60h write sector address with [a6,a1,a0]:[0,1,0] data: 40h read at sector address with [a6,a1,a0]:[0,1,0] wait 150us reset plscnt=1 temporary unprotect mode reset#=vih write reset cmd sector protect done device fail temporary unprotect mode retry count +1 first cmd=60h? data=01h? retry count=25? ye s ye s ye s ye s no no no no protect another sector?
46 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 15. chip unprotect algorithm with reset#=vhv write [a6,a1,a0]:[1,1,0] data: 60h write [a6,a1,a0]:[1,1,0] data: 40h read [a6,a1,a0]:[1,1,0] wait 15ms temporary unprotect reset#=vih write reset cmd chip unprotect done retry count +1 device fail all sectors protected? data=00h? last sector verified? retry count=1000? yes yes yes no no no yes protect all sectors start retry count=0 reset#=vhv wait 1us temporary unprotect first cmd=60h? yes no no
47 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 16. temporary sector unprotect waveform table 5. temporary sector unprotect reset# ce# we# ry/by# trpvhh 10v vhv 0 or vih vil or vih tvhhwl trpvhh program or erase command sequence parameter alt description condition speed unit trpvhh tvidr reset# rise time to vhv and vhv fall time to reset# min 500 ns tvhhwl trsp reset# vhv to we# low min 4 us
48 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 17. temporary sector unprotect flowchart notes: 1. temporary unprotect all protected sectors vhv=9.5~10.5v. 2. after leaving temporary unprotect mode, the previously protected sectors are again protected. start apply reset# pin vhv volt enter program or erase mode (1) remove vhv volt from reset# (2) reset# = vih completed temporary sector unprotected mode mode operation completed
49 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 18. silicon id read timing waveform ta a tce ta a to e to h to h tdf data out 00c2h 22c4h (top boot) 2249h (bottom boot) vhv vih vil a9 add ce# a1 oe# we# a0 data out data q15-q0 vih vil vih vil vih vil vih vil vih vil a6 vih vil vih vil vih vil
50 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b write operation status figure 19. data# polling timing waveform (during automatic algorithm) tdf tce tch to e toeh to h ce# oe# we# q7 q6-q0 ry/by# tbusy status data status data complement complement true valid data ta a trc address va va high z high z valid data true
51 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 20. data# polling algorithm read q7~q0 at valid address (note 1) read q7~q0 at valid address start q7 = data# ? q5 = 1 ? q7 = data# ? (note 2) fail pass no no no ye s ye s ye s notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 should be rechecked even q5="1" because q7 may change simultaneously with q5.
52 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b figure 21. toggle bit timing waveform (during automatic algorithm) tdf tce tch to e toeh ta a trc to h address ce# oe# we# q6/q2 ry/by# tbusy valid status (first read) valid status (second read) (stops toggling) valid data va va va va : valid address va valid data
53 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1". figure 22. toggle bit algorithm read q7-q0 twice q5 = 1? read q7~q0 twice program/erase fail write reset cmd program/erase completed q6 toggle ? q6 toggle ? no (note 1) yes no no yes yes start
54 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power- up. if the timing in the fgure is ignored, the device may not operate correctly . figure a. ac timing at device power-up vcc address ce# we# oe# data tvr taa tr or tf tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil vih vil voh high z vol wp#/acc valid ouput valid address tvcs tr toe tf tr symbol parameter min. max. unit tvr vcc rise time 20 500000 us/v tr input signal rise time 20 us/v tf input signal fall time 20 us/v tvcs vcc setup time 200 us
55 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b erase and programming performance min. max. input voltage difference with gnd on all pins except i/o pins -1.0v 10.5v input voltage difference with gnd on all i/o pins -1.0v 1.5 x vcc vcc current -100ma +100ma all pins included except vcc. test conditions: vcc = 3.0v, one pin per testing parameter limits units min. typ. max. chip erase time 15 32 sec sector erase time 0.7 2 sec erase/program cycles 100,000 cycles chip programming time 12 36 sec word program time 11 360 us accelerated program time 7 210 us latch-up characteristics parameter symbol parameter description test set typ max unit cin2 control pin capacitance vin=0 7.5 9 pf cout output capacitance vout=0 8.5 12 pf cin input capacitance vin=0 6 7.5 pf tsop/bga pin capacitance notes: 1. erase/program cycle comply with jedec jesd-47e & a117a standand. data retention parameter condition min. max. unit data retention 55?c 20 years
56 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b ordering information part no. access time (ns) ball pitch/ ball size package remark mx29lv161dtti-90g 90 48 pin tsop (normal type) pb free mx29lv161dbti-90g 90 48 pin tsop (normal type) pb free mx29lv161dtxbi-90g 90 0.8mm/0.3mm 48 ball bga (ball size:0.3mm) pb free mx29lv161dbxbi-90g 90 0.8mm/0.3mm 48 ball bga (ball size:0.3mm) pb free mx29lv161dtgbi-90g 90 48 ball xflga (4 x 6 x 0.5mm) pb free mx29lv161dbgbi-90g 90 48 ball xflga (4 x 6 x 0.5mm) pb free mx29lv161dtxhi-90g 90 48 ball wfbga (4 x 6 x 0.75mm) pb free mx29lv161dbxhi-90g 90 48 ball wfbga (4 x 6 x 0.75mm) pb free
57 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b part name description mx 29 lv 90 d t t i g option: g: pb-free package speed: 90: 90ns temperature range: i: industrial (-40c to 85c) package: t: tsop x: fbga (csp) xh: wfbga - 4 x 6 x 0.75mm, pitch 0.5mm, 0.3mm ball gb: xflga - 4 x 6 x 0.5mm, pitch 0.5mm, 0.25mm ball boot block type: t: top boot b: bottom boot revision: d density & mode: 161: 16mb, x16 boot block type: lv: 3v device: 29:flash xb - 6 x 8 x 1.2mm, pitch 0.8mm, 0.3mm ball 161
58 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b package information
59 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b 48-ball tfbga (for mx29lv161d txbi/bxbi)
60 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b 48-ball wfbga (for mx29lv161d txhi/bxhi)
61 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b 48-ball xflga (for mx29lv161d tgbi/bgbi)
62 p/n:pm1359 rev. 1.0, jun. 03, 2010 mx29lv161d t/b revision history revision no. description page date 0.01 1. modifed pin confgurations -- 48-ball wfbga/xflga from p7 oct/17/2007 ry/by# to nc 2. modifed output load capacitance,cl from 100pf to 30pf p30 3. added wp#/acc function p5,7,8,9,14 p17,30,32,41 p55 4. modifed output load capacitance,cl from 100pf to 30pf p31 0.02 1. modifed tvcs from 100us to 200us p54 oct/23/2007 0.03 1. table 4-4. cfi added address 4d~4f p28 nov/29/2007 0.04 1. modifed tvcs from 100us to 200us p32 dec/07/2007 0.05 1. modifed table 4-4. address 4d data from 00b5 to 00a5; p28 dec/18/2007 address 4e data from 00c5 to 00b5 0.06 1. swapped a19 with vi/o ball location p8 jan/15/2008 0.07 1. modifed wfbga & xflga for wp#/acc pin p8 jan/29/2008 0.08 1. changed toe spec from 30ns to 40ns p32 jun/16/2008 2. revised vhv data from 10.5v~11.5v to 9.5v~10.5v p30,41,47,48 3. changed vol/voh spec p30 4. modifed switching test circuit p31 5. changed output load capacitance, cl from 50pf to 30pf p31 0.09 1. changed icr1 from 7ma(typ.) to 5ma(typ.) p5,30 jul/29/2008 1.0 1. removed "advanced information" all jun/03/2010 2. revised data retention from 10 years to 20 years p5-6,55 3. added tsrw (ac/waveform, min. 45ns) p32,34 4. added wp#acc pin note p9
mx29lv161d t/b macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and mili - tary application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. copyright? macronix international co., ltd. 2007~2010. all rights reserved. macronix, mxic, mxic logo, mx logo, are trademarks or registered trademarks of macronix international co., ltd. the names and brands of other companies are for identifcation purposes only and may be claimed as the property of the respective companies. for the contact and order information, please visit macronixs web site at: http://www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice.

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